As semiconductor processes continue to scale downwards, e.g., shrink, the desired spacing between features (i.e., the pitch) also becomes smaller. To this end, in the smaller technology nodes it becomes ever more difficult to fabricate features due to the critical dimension (CD) scaling and process capabilities.
For example, in the fabrication of gate structures, the gate height after an interlevel dielectric fill is set by the spacers of the gate structure and an etch stop line. However, the gate structures can suffer from gate height loss after pulling of the dummy gate, gate cut and replacement metal gate processes. This loss in gate height can result in a short between the metal material of the gate structures and the metal material used to form the source and drain contacts.